High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

This paper describes the impression of low-k/high-k dielectric on performance Double Gate Junction less (DG-JL) MOSFET. An analytical model threshold voltage DG-JLFET has been presented. Poisson’s equation is solved using parabolic approximation to find out voltage. The effect high-k various parameters N-type explored. comparative analysis carried between conventional gate oxide, multi oxide and in terms Drain Induced Barrier Lowering (DIBL), voltage, figure merit (ION/IOFF) sub-threshold slope (SS). shown superlative as compared others. results are further analyzed for device structures. with HfO2 exhibits excellent attainment by mitigating Short Channel Effects (SCEs). significant reduction off current makes suitable ultra-low power applications. There a 61.9 % 34.29 improvement proposed other devices. simulation Silvaco TCAD tool.